1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) panel, and more particularly, to an LCD panel and method for forming the same where a transparent conducting layer is directly connected to a data line and a thin film transistor.
2. Description of Prior Art
An advanced monitor with multiple functions is an important feature for use in current consumer electronic products. Liquid crystal displays (LCDs) which are colorful monitors with high resolution are widely used in various electronic products such as monitors for mobile phones, personal digital assistants (PDAs), digital cameras, laptop computers, and notebook computers.
Please refer to FIG. 1 showing a layout of a pixel unit of a conventional liquid crystal display (LCD). The LCD includes a gate line 1, a data line 3, a common line 2, an active layer 6, a pixel electrode 9, and a storage capacitor 10. The pixel electrode, e.g. a transparent conducting layer made of indium tin oxide (ITO), is connected to the data line 3 through a via hole 5.
Generally speaking, a pixel corresponds to a scan line and a data line. Referring to FIG. 2 showing a cross section view along a line ABC shown in FIG. 1, the scan line 1 and a common line 2 is formed by a first metal layer, while the data line 3, a drain 4, and a source 5 are made of a second metal layer. Upon voltage delivered by the scan line 1 in an excess of a threshold voltage, data voltage from the data line 9 of the second metal layer M2 is delivered to the pixel electrode 9 by way of the second metal layer M2, the active layer 6, the second metal layer M2, the transparent conducting layer 7 on the via hole 8, and the pixel electrode 9. The pixel electrode 9 is charged based on voltage level of the data voltage, accordingly. As illustrated in the cross section view of FIG. 2, the common line 2 and the scan line 1 electrically connected with a gate which are formed by the first metal layer, the isolator layer 12, an ohmic connecting layer 13, the active layer 6, the source 5 and the drain 4 of a thin film transistor (TFT) which are formed by the second metal layer, the transparent conducting layer 7, and the passivation layer 11 are shown.
Currently, a development of the liquid crystal display technology is in a tendency to a LCD panel with a large frame and a high display quality. For a purpose of a high display quality, one approach is to increment a frame rate of the LCD panel. However, the current LCD panel having multiple transistors arranged in an active matrix is a standardized structure, which is a disadvantage of raising the frame rate. Please refer to FIG. 3 depicting a conventional structure of the active matrix circuitry. For example, for the LCD panel with a 1920×1080 resolution and a frame rate of 120 Hz in normal, a maximum effective charging time period tcharging—120Hz (without taking a blanking time period into consideration) is calculated as:
      t                  c        ⁢        harging        ⁢        _            ⁢      120      ⁢                          ⁢      Hz        =            1000000              120        ×        1080              ≈          7.7      ⁢                        (          µsec          )                .            By contrast, under a frame rate of 240 Hz, the maximum effective charging time period approximates to as 3.86μ seconds. It is too short to charge to required voltage level if considering RC delay and charging performance of TFT. In order to solve this problem, another approach is to double a number of data lines in the LCD panel. As shown in FIG. 4 illustrating a structure of an active matrix circuitry operating with a higher frame rate, two pixel electrodes on two neighboring rows are charged to predefined voltage levels in one gate-on time period with two data lines. As compared, two pixel electrodes on two neighboring rows of the traditional active matrix circuitry are charged to predefined voltage levels in two gate-on time periods. Even if operating in 240 Hz, the maximum effective charging time period of the active matrix circuitry shown in FIG. 4 is still 7.7μ seconds.
Refer to FIG. 5 showing a layout of three pixel electrodes on three consecutive rows to be simultaneously charged in one turn-on time period. Similar to above mentioned principle, three pixel electrodes 9a-9c on three consecutive rows to be simultaneously charged in one turn-on time period is realized by configuring a pair of via holes (circled area in dotted line) and a transparent conducting layer to link three neighboring data lines 3a-3c, so that data signal from the middle data line 3b can be transmitted to sources of the corresponding TFTs. Such design reduces a aperture ratio and degrades display brightness.
In sum, it is proper for implementing two pixel electrodes on two neighboring rows to be simultaneously charged in one turn-on time period. In other words, for keeping the aperture ratio and display brightness, the frame rate is at least 240 Hz considering a RC delay and a charging performance of a TFT.
Therefore, it is necessary for providing a novelty LCD panel capable of raising frame rate to solve the problems existing in prior art.